The disclosure relates to a memory device, and more particularly, to a memory device including a dynamic voltage and frequency scaling (DVFS) switch and a method of operating the same.
A capacity and speed of a semiconductor memory device widely used in a high performance electronic system are increasing. As an example of the semiconductor memory device, dynamic random-access memory (DRAM) is a volatile memory and determines data by charges stored in a capacitor.
DRAM may perform internal operations by using various levels of power voltages. In addition, as a dynamic voltage and frequency scaling (DVFS) technique is applied, the power voltages and an operation frequency may be controlled in various operation modes of the DRAM. In addition, for power voltage management, the DRAM may include a plurality of power rails and switches connected to the power rails. In accordance with a connection structure of switches, a common node (or a short node) to which two power voltages are connected may exist. At this time, during initial driving of the DRAM, before a level of a power voltage is stabilized, an erroneous operation of switching may occur. In addition, as peak current flows to the common node, there is a probability of element damage.